A digital filter is a software or a specially designed electronic circuit processing discrete digital signal samples to perform a desired transfer function operation on said signal. The Z transfer function of a digital, i.e. discrete time, FIR (Finite Impulse Response) filter has the generic form ##EQU1## where H(z) is the transfer function of the filter, Y(z) and X(z) represent the output and input of the filter respectively, a.sub.i represent constant coefficients, i.e. tap coefficients, and z.sup.-i represents a delay of i samples. The properties of a FIR filter are solely dependent on the tap coefficients a.sub.i, and thus determination of these coefficients is required in order to obtain the desired characteristics for the filter. There are several methods for determining the coefficients. The non-recursive discrete time filter in accordance with equation (1) is normally represented as a block diagram as shown in FIGS. 1 and 2. FIG. 1 illustrates a direct-type FIR (Finite Impulse Response) filter and FIG. 2 a transposed FIR filter. The filtering function in accordance with equation (1) can be realized by both types of discrete time filter, but the present invention relates to a direct-type FIR filter according to FIG. 1. As is apparent from FIGS. 1 and 2, the discrete time filter is illustrated as a block diagram wherein square blocks 1 perform delaying of the information by one sample z.sup.-1, triangular blocks 2 represent multiplication operations, and circles 3 represent adders.
As stated previously, the characteristics of the filter are dependent on the values of the tap coefficients a.sub.i. Prior art direct-type FIR filters exist in which a discrete multiplier unit for each tap coefficient is employed. The drawback of this approach is the large number of multiplier units required, which occupy a considerable area on a semiconductor chip when embodied as an integrated circuit and are therefore costly. A prior art approach is known in which the tap coefficients are simple sums of powers of two, i.e. the coefficients are limited to the form 2.sup.-a +2.sup.-b +2.sup.-c. Such an approach is attended by the drawback of limitations in the possible coefficients to be realized. These limitations can substantially complicate the realization of the desired signal processing function H(z).
Still another prior art solution entails the use of a fast multiplier and memory for realizing the filter. Such a solution is illustrated in FIG. 3, wherein the necessary delays z.sup.-1 are generated by buffering the values of the input signal X(z) into a RAM memory 41 prior to inputting them to a multiplier 42, in which they are multiplied by coefficients a.sub.i derived from a ROM memory. Thereafter the multiplication results are supplied to an adder 44 wherein they are summed with the filter output Y(z). The drawback of such a solution is the chip area occupied by the fast multiplier unit 42. Further drawbacks include the high power consumption of the multiplier unit 42 and, in certain applications, the electromagnetic interference produced thereby in other circuitry. Furthermore, on account of the limited speed of the multiplier unit, only a limited number of coefficients a.sub.i can be realized with one multiplier unit. Complex structures require several multiplier units and a complex control logic.